Physical Design Engineer

The key to this job is STA or static timing analysis; we use a tool called Primetime

You will be responsible for all aspects of physical implementation from RTL to GDS, including  RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout.   Interface with other design groups to ensure time to market and quality of results. You will also participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation.

Benefits - Full

Relocation Assistance Available - Yes

Bonus Eligible - Yes

Candidate Details

5+ to 7 years experience

Minimum Education - Bachelor's Degree

Skills and Certifications [note: required]

have the worked on/written timing constraints

experience with clock tree synthesis

scan insertion / dft

rtl logic

Screening Questions

Ideal Candidate - This position requires a BSEE/MSEE and 5+ years industry experience in a Logic design or Physical Design position.  Candidate should preferably have strong knowledge of RTL design and must be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter, Primetime, Conformal LEC, and ATPG. Ideal candidate will also have working knowledge of scan insertion, and ATPG.  Must have good communication, teamwork, and debug/analysis skills for designs, library and technology files.