Design Verification Engineer

Responsible for functional verification of mixed-signal audio CODECs. Detailed responsibilities include but are not limited to: verification planning, testbench development, failure analysis and resolution, coverage analysis and population, digital/mixed-signal modeling, directed/constraint-random test generation, and flow development. Candidates must work closely with digital/analog designers, applications engineers and manufacturing test to support both pre-silicon verification and post silicon validation efforts.

Skills/Experience - Requires a MSEE/MSCS and 5 years of verification experience preferably in mixed signal products. Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera, e) required. The candidate must have solid scripting skills with Matlab, Perl, Unix/Linux shell, TCL, and must be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS. Knowledge of signal processing and Verilog Assertions are also a plus. The proven ability to create, evaluate, debug, and improve a verification process is essential for this position.

Base Salary - $90,000 to $125,000

Additional Compensation - $7,500 to $25,000

5+ to 7 years experience

Minimum Education - Master's Degree

Willingness to Travel - Occasionally

MUST HAVE

presently doing verification on digital, analog and mixed signal IC's

Verilog or System Verilog experience

Ideal Candidate has worked at TI, Maxim, Analog Devices, Silicon Labs, Qualcomm, IDT, Broadcom